1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and abrasive liquid used therein. More particularly, the present invention relates to a fabrication method of a semiconductor device including the step of planarizing an insulation film, and abrasive liquid used therein.
2. Description of the Background Art
Reducing the size of interconnections and providing multilayers are now required to further increase the integration density of semiconductor integrated circuit devices. An interlayer insulation film is provided between each interconnection to obtain a multilayer structure of the interconnection. If the surface of this interlayer insulation film is not planar, a step-graded portion will be generated at the interconnection formed above the interlayer insulation film. This will cause defects such as disconnection.
Therefore, the surface of the interlayer insulation film (the surface of the device) must be made as flat as possible. The technique to planarize the surface of the device is called planarization. This planarization technique has become important in reducing the size and providing multilayers of the interconnection.
The following two methods are known as conventional planarization techniques. As the first method, planarization using an SOG (Spin On Glass) film is known. The technique of planarization using an SOG film will be described hereinafter.
An SOG film is known as the most commonly used interlayer insulation film in the planarization art. In recent years, development in the planarization technique taking advantage of fluidity of a material of the interlayer insulation film is particularly noticeable.
An xe2x80x9cSOG filmxe2x80x9d is a generic term of a film mainly composed of a solution in which a silicon compound is dissolved in an organic solvent, and silicon dioxide formed from that solution. In forming an SOG film, first a solution having a silicon compound dissolved in an organic solvent is applied in droplets while the substrate is rotated. By this rotation, the solution coating is provided so as to alleviate the step-graded portion on the substrate corresponding to the interconnection. More specifically, the coating is formed thick at the concave portion and thin at the convex portion on the substrate. Thus, the solution coating results in a planarized surface.
Heat treatment is then applied to vaporize the organic solvent. Also, polymerization proceeds to result in a planarized SOG film at the surface.
An SOG film is typically classified into an inorganic SOG film that does not include any organic component in the silicon compound, as represented by the following general formula (1), and an organic SOG film including an organic component in a silicon compound, as represented by the following general formula (2).
[SiO2]nxe2x80x83xe2x80x83(1) 
[Rx SiOY]nxe2x80x83xe2x80x83(2) 
(n, X, Y: integer; R: alkyl group or aryl group
An inorganic SOG film has a disadvantage that it is more brittle than a silicon oxide film formed by CVD (Chemical Vapor Deposition) in addition to being highly hygroscopic. For example, a crack is easily generated during the heat treatment in an inorganic SOG film when thicker than 0.5 xcexcm.
In contrast, although an organic SOG film is highly hygroscopic, the organic SOG film is suppressed in generation of a crack during heat treatment. Therefore, the organic SOG film can be formed to a thickness to approximately 0.5-1.0 xcexcm. That is: The usage of an organic SOG film allows the formation of a thicker interlayer insulation film. Therefore, sufficient planarization can be achieved even for a great step-graded portion on a substrate.
The second method of planarization employs chemical mechanical polishing (referred to as CMP hereinafter).
The CMP method is a process including chemical action in addition to mechanical polishing. For example, after a thick insulation film such as of silicon oxide is formed on a substrate by plasma CVD and the like, the insulation film is polished down to a predetermined film thickness by CMP. In this CMP method, polishing is carried out while applying an abrasive with colloidal silica as the main component.
Planarization using an SOG film is advantageous over one using an insulation film deposited only by CVD in that favorable planarization is achieved. However, this planarization of the current level in which complete planarization cannot be achieved is not sufficient to meet the potential high standard for an interlayer insulation film as microfabrication proceeds and the scale of integration increases since an SOG film is formed from liquid. It is therefore difficult to completely correspond to the microfabrication and high integration of the devices.
Planarization according to CMP is advantageous over planarization using SOG film in that planarization of a higher level can be achieved. However, when only an insulation film (for example, a silicon oxide film) formed by CVD is used as an interlayer insulation film as in the conventional case, it is difficult to embed an insulation film in microminiaturized interconnection without any gap. A void may be generated. Even if the interconnections are filled with an insulation film without any gap, the capacitance between the interconnections will become greater since the insulation film formed by CVD has a high relative dielectric constant. This causes the problem that the operating speed of the LSI will be degraded due to RC delay.
An approach of achieving a favorable planarized surface of an appropriate level by planarization using an SOG film, and then polishing the planarized surface by CMP for further planarization is conventionally known.
However, this process of polishing an SOG film by CMP induces problems set forth in the following. The polishing rate of an SOG film by CMP is lower than that of the case where an insulation film formed by CVD is polished by CMP. Therefore, the throughput is reduced to increase the cost for fabrication. There is also a problem that a defect such as a scratch (generated during polishing) is easily generated at the surface of the SOG film.
An object of the present invention is to provide a fabrication method of a semiconductor device that allows improvement in planarization and polishing rate of an insulation film.
Another object of the present invention is to provide a fabrication method of a semiconductor device that can effectively prevent a defect from being generated in an insulation film during polishing working thereof.
According to an aspect of the invention, a fabrication method of a semiconductor device includes the following steps. First, impurities are introduced into a first insulation film. Then, planarization is carried out by polishing the surface of the first insulation film in which impurities are introduced. By carrying out polishing after impurities are introduced into the first insulation film, the polishing rate of the first insulation film by CMP is improved substantially to a level equal to the polishing rate of a silicon oxide film formed by CVD. Accordingly, the polish workability can be improved. Since polishing of the first insulation film is promoted by introduction of impurities thereto, the problem of generation of a defect such as a scratch during polishing of the first insulation film can be prevented effectively.
According to another aspect of the present invention, a method of fabricating a semiconductor device includes the following steps. A first insulation film is formed on a substrate. Then, a second insulation film is formed on the first insulation film. Impurities are introduced to at least the surface of the first insulation film before or after formation of the second insulation film. Planarization is achieved by polishing at least the second insulation film. By introducing impurities to at least the surface of the first insulation film, the portion where impurities are introduced has a polishing rate by CMP as high as that of a silicon oxide film formed by CVD. As a result, the polish workability of the first insulation film is improved. Also, a defect such as a scratch is not easily generated. In the fabrication method of the present aspect, the step of planarization can be carried out by polishing the first and second insulation films. The second insulation film can include a silicon oxide film formed by plasma CVD. Also, a photoresist film can be formed on the surface of a device before introducing impurities to the first insulation film, and introduce impurities to the first insulation film via the photoresist film. As a result, the depth of the introduced impurity is substantially set uniform since impurities are introduced via a photoresist that has an extremely flat surface. This provides the advantage that the boundary depth between the portion of the first insulation film where impurities are introduced and the portion where impurities are not introduced became uniform so that the end point for polishing can easily be detected by virtue of the portion without impurity introduced serving as a stopper with respect to polishing. In the fabrication method of the present aspect, a third insulation film can be formed on the surface of the device after polishing, and a fourth insulation film can be formed on the surface of the device prior to formation of the first insulation film. The formation of the third and fourth insulation films provides the advantage of increasing the mechanical strength of the insulation film. Also, the first insulation film can include a silicon oxide film material consisting of at least 1% of carbon in the fabrication method of the present aspect. Furthermore, the first insulation film can include a material having a contact angle of 30xc2x0 and below of purified water with respect to the first insulation film. The first insulation film can also include an inorganic SOG film. The above-described polishing can be carried out according to chemical mechanical polishing. In this case, a surfactant is preferably used in the polishing step. It is also preferable to introduce impurities to the first insulation film by implantation. In this case, the impurities preferably include at least one element selected from the group consisting of argon, boron, nitrogen and phosphorus.
A method of fabricating a semiconductor device according to another aspect of the invention includes the following steps. First, a first insulation film is formed on an substrate. Impurities are introduced into at least a surface of the first insulation film. Planarization is effected by polishing the first insulation film. The introduction of impurities to at least the surface of the first insulation film provides the advantage that the portion of the first insulation film in which impurities are introduced is improved in the polishing rate. Also, generation of a defect such as a scratch during polishing can be prevented effectively. According to the fabrication method of the present aspect, impurities can be introduced only to the surface of the first insulation film. Also, a third insulation film can be formed on the surface of the device after polishing, or a fourth insulation film can be formed on the surface of the device before the first insulation film is formed. Formation of the third and fourth insulation films provides the advantage that the mechanical strength of the entire insulation film is improved. The first insulation film can include a silicon oxide material containing at least 1% of carbon. The first insulation film can include a material having a contact angle of not more than 30xc2x0 of purified water with respect to the film. The first insulation film can include an inorganic SOG film. Also, the above polishing step can be carried out by chemical mechanical polishing. In this case, an abrasive liquid including a surfactant is preferably used. Impurities can be introduced into the first insulation film by implantation. In this case, the impurities preferably include at least one element selected from the group consisting of argon, boron, nitrogen and phosphorus.
A fabrication method of a semiconductor device according to still another aspect of the present invention includes the following steps. First, a first insulation film is formed on a substrate. A second insulation film is formed on the first insulation film. Planarization is effected by polishing at least the second insulation film using abrasive liquid including a surfactant according to chemical mechanical polishing. By using abrasive liquid including a surfactant in chemical mechanical polishing, abrasive liquid of favorable wettability can be obtained to carry out the polishing work more favorably. In this case, the surfactant is preferably a fatty acid compound. Impurities can be introduced to the first insulation film after this polishing step.
The abrasive liquid according to still another aspect of the present invention includes at least a surfactant used in a chemical mechanical polishing process. In this case, the surfactant preferably includes a fatty acid compound.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.